1. Field of the Invention
The present invention relates to fabricating a 3-D integrated circuit.
2. Description of the Related Art
Due to the high cost of silicon real estate and the need to create ever smaller memory devices, monolithic 3-D memory devices have become increasingly popular. Such devices can include multiple levels of interconnected memory cells. Examples of this technology can be found in U.S. 2005/0098800, titled “Nonvolatile memory cell comprising a reduced height vertical diode,” published May 12, 2005, and U.S. Pat. No. 6,952,030, titled “High-density three-dimensional memory cell”, issued Oct. 4, 2005, both of which are incorporated herein by reference. In such devices, the memory cells can be formed as diodes in polysilicon layers, while conductive rails which interconnect the memory cells can be formed by etching oxide layers and depositing a conductive material. However, various challenges are encountered in forming interconnects between the layers of such memory devices and other 3-D integrated circuits. In particular, as 3-D monolithic integrated circuits push minimum feature sizes and etch and fill aspect ratios to the limit, conventional fabrication techniques have been found to be inadequate. For example, etching of relatively deep vias and trenches between layers can be problematic.